Description
Revision Standard – Active.A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.
Product Details
- Published:
- 10/12/2022
- ISBN(s):
- 9781504488662, 9781504488679, 9781504490436
- Number of Pages:
- 154
- File Size:
- 1 file , 4.4 MB
- Product Code(s):
- STD25531, STDPD25531, STDPL25687
- Note:
- This product is unavailable in Russia, Ukraine, Belarus
